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ADuC7060
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
PLL Off
Wakeup from Interrupt
Internal PLL Lock Time
CD = 0
66
1
μs
ms
POWER REQUIREMENTS
Power Supply Voltages
DVDD (±5%)
AVDD (±5%)
2.375
2.375
2.5
2.5
2.625
2.625
V
V
Power Consumption
I DD (MCU Normal Mode) 18
MCU clock rate = 10.24 MHz,
6
10
mA
ADC on
MCU clock rate = 1.28 MHz,
ADC on, DAC off
2.8
mA
I DD (MCU Powered Down) 1
Full temperature range
Reduced temperature range
55
55
350
120
μA
μA
?40°C to +85°C
I DD (Primary ADC)
PGA enabled, normal mode/low
0.8/0.3
mA
power mode
I DD (Auxiliary ADC)
Normal mode/low power mode
0.3/0.1
mA
1
2
3
4
5
6
7
8
9
These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
Valid for primary ADC gain setting of PGA = 4 to 64.
Tested at gain range = 4 after initial offset calibration.
Measured with an internal short. A system zero-scale calibration removes this error.
Measured with an internal short.
These numbers do not include internal reference temperature drift.
Factory calibrated at gain = 1.
System calibration at a specific gain range removes the error at this gain range.
Measured using an external reference.
10
11
12
13
14
15
16
17
18
Limited by the minimum absolute input voltage range.
Measured using the box method.
References up to AVDD are accommodated by setting ADC0CON Bit 12.
Reference DAC linearity is calculated using a reduced code range of 171 to 4095.
Reference DAC linearity is calculated using a reduced code range of 2731 to 65,535.
Die temperature.
Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at ?40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
Retention lifetime equivalent at junction temperature (T J ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
Rev. 0 | Page 8 of 100
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